Shift Left Performance Verification using Formal Methods for ML ASICs
TimeWednesday, July 13th5pm - 6pm PDT
LocationLevel 2 Exhibit Hall
Engineering Track Poster
DescriptionUsage of Formal Tools has proliferated over the last decade with Formal methods being used extensively for functional verification. Performance analysis, bubble absence & bottleneck analysis, however, is still done the old way. System level Performance verification needs a deep understanding of architecture and pipeline structure with huge run times, heavy iteration penalty as it can be run on Emulator or scaled RTL designs in simulation.
We show how Formal methods can come to the rescue by breaking the problem at block and sub-block level protocol behavior.
We show why Simulation and Emulation will start performance after full functional bring up and how formal approach can help it analyze much earlier.
We also describe various methods used for formal convergence like Abstraction, Scaling, modeling. We also talk about effort required and number of bugs found using this approach.
We talk about our plans to use the same methodology for many other blocks and subsystems in a wide range of designs.