Power-Thermal Co-simulation for More Accurately DC IRDrop and temperature distribution of GPGPU’s PCB and Package
TimeMonday, July 11th5pm - 6pm PDT
LocationLevel 2 Exhibit Hall
Event Type
Engineering Track Poster
Engineering Tracks
Back-End Design
Embedded Systems
Front-End Design
DescriptionThe power delivery network of GPGPU faces more challenge as the power are continuously increasing for more computing cores integrated into GPGPU.
It will induce the un-even temperature distribution from PCB, substrate to chip level due to I2R loss along the PDN.
The temperature hotspot will be more prone to appear if the PDN is not well optimized. It will cause EM/IR issues that will have great impact on the lifetime.
In turn, the temperature will have negative influence on electrical conductivity. Typically, DC IRdrop simulation will use electrical conductivity under the average temperature is 85C. Previously it is the conservative approach as the current is less than 200A at high voltage level. As Moore’s Law move forward, the supply voltage is continuously decreased to 0.75V for N7 process. For air-cooled condition, high-performance GPGPU will demand more current > 300A for sustaining the performance. It will draw ~800A if GPGPU changed to liquid-cooled condition. These trends will lead to more I2R loss along the PDN that will make PCB/substrate hotter than 85C average. It is too optimistic for DC IRDrop if it uses traditional assumption.
Ansys provides the great opportunity on iterative power-thermal co-simulation with SIwave and Icepak. The paper will outline the key process on how to build power-thermal co-simulation model. Compared to traditional method, it achieves more accurate simulation results to guide both PDN optimization and thermal/mechanical solution.