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Presentation

Billion Instance Timing Sign-off
TimeMonday, July 11th4:30pm - 4:40pm PDT
LocationDAC Pavilion, Level 2 Exhibit Hall
Event Type
DAC Pavilion Gladiator Arena Poster Battle
Engineering Track Poster
Engineering Tracks
Topics
Back-End Design
Embedded Systems
Front-End Design
IP
DescriptionDesign data volume continues to grow with each technology node. Reticle-sized designs with 1B instances are becoming commonplace. Our team has worked with several of these designs. This presentation will give an overview of some of the techniques necessary and challenges encountered when processing these large designs. Techniques include distributed computing (where the model is split across many hosts), hierarchical abstraction (where lower levels are abstracted for use at the parent), and partial design timing for faster closure. We will look at the effect these techniques have on the schedule and necessary IT resources. Some of the potential runtime bottlenecks will also be considered along with possible solutions.