Overcoming IR Challenges for reticle sized ASIC in new architecture and advanced node
TimeMonday, July 11th5pm - 6pm PDT
LocationLevel 2 Exhibit Hall
Event Type
Engineering Track Poster
Engineering Tracks
Back-End Design
Embedded Systems
Front-End Design
DescriptionAs technology nodes have advanced we have seen significant area and performance improvement but the same level of scaling has not been observed for power and parasitic. For a large chip size is a concern but aiming for a highly active chip leads to power, current density, and thermal gradient challenges add to tool based limitations. If we have a new architecture on top of these concerns, then power grid design, power as well as IR analysis methodology poses a range of issues. The power and IR team need to be proactive in such cases to design the grid and prepare the methodology for analysis and convergence to meet the requirements. In this paper we describe our experience through all these challenges on a reticle sized advanced node new architecture-based design. We signed off on our specifications by designing a robust adaptive power grid with a mixed vector and vectorless IR analysis. The paper explains how we worked on correlation at different levels of the design which reduced our turnaround time for addressing the violations. We also share our techniques to resolve the violations seen in designs with diverse complexities.