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Presentation

Back End of Line Process-aware Static Timing Analysis
TimeMonday, July 11th5pm - 6pm PDT
LocationLevel 2 Exhibit Hall
Event Type
Engineering Track Poster
Engineering Tracks
Topics
AI
Back-End Design
Cloud
Embedded Systems
Front-End Design
IP
DescriptionWe introduced a way to explore BEOL sweet spot without extensive DOEs in the manufacture development stages. BEOL sweet spot exploration is implemented based on machine learning using hyper-parameter optimization. With proposed methodology, design suitable BEOL sweet spot is searched. It achieved up to 3% maximum frequency improvement in the real design. Additionally, timing optimization flow is validated using 5nm and it showed good accuracy.