Library Analytics and Library Partitioning [LALP] for PPA Efficiency
TimeMonday, July 11th5pm - 6pm PDT
LocationLevel 2 Exhibit Hall
Event Type
Engineering Track Poster
Engineering Tracks
Back-End Design
Embedded Systems
Front-End Design
DescriptionLibrary optimization for better Performance-Power-Area optimization is an area of active interest in SOC design community. Strategic segmentation of library space can unlock additional benefits in terms of PPA, runtime or other metrics. This work demonstrates a state-of-the art CAD infrastructure that offers multi-dimensional analytics from standard cell library and slicing based library segmentation methodology. Study of eight complex design partitions from a 10nm SOC sub-system with fastest clock of 1 GHz+ shows guided library partitioning methodology can offer more than 40% performance improvement within 15% power degradation and up to 10% performance improvement with no appreciable Power impact.