Enabling a 20B-transistor Chip with Unit Level Timing Abstraction
TimeMonday, July 11th5pm - 6pm PDT
LocationLevel 2 Exhibit Hall
Engineering Track Poster
DescriptionWill describe the use of unit level boundary timing models to reduce the size of chip level timing graphs used in the latest IBM processor designs. Macro level timing models have been in use for a number of processor projects, present the technical challenges unique to unit level designs and tool/methodology enablement required. Additionally, include the test and qualification work to ensure the new flow can be integrated without disruption into projects.