Clock Spine Automation for Clock Latency and Turn-Around-Time Reduction
TimeMonday, July 11th5pm - 6pm PDT
LocationLevel 2 Exhibit Hall
Event Type
Engineering Track Poster
Engineering Tracks
Back-End Design
Embedded Systems
Front-End Design
DescriptionAt lower process technologies higher variability can increase clock insertion delay and skew significantly. While clock mesh is better option to achieve close to zero skew and minimize the variability effects, it is resource intensive and high effort to implement. For the streamlined data flow design at long range physical area such as channel with locally synchronous timing behavior(e.g., NoC bus routing), clock spine would be a suitable solution. Clock spine is a feasible alternative to reduce local latency without significant drain on physical resources and power increase. However, since the clock spine is based on MSCTS, the design exploration time can be greatly increased to find optimized clock structure specification. Therefore, to get better timing and clock QoR and reduce TAT, clock spine automation method was proposed in this material.