On-Chip PDN-Aware Simulation Methodology with RC Network Reduction
TimeMonday, July 11th5pm - 6pm PDT
LocationLevel 2 Exhibit Hall
Event Type
Engineering Track Poster
Engineering Tracks
Back-End Design
Embedded Systems
Front-End Design
DescriptionWith increasing clock frequency and reducing power supply voltage in high speed memory interface, demands for co-simulation of Signal Integrity(SI) and Power Integrity(PI) has been growing to ensure robust timing performance. However, there has been a challenge for a simulation considering both Signal Distribution Network(SDN) and Power Distribution Network(PDN) due to extremely huge RC network from PDN and long simulation time. In this paper we propose a SI/PI co-simulation methodology based on reduction of RC network. We propose the technique that partially extracts RC network based on the selected circuit and power network. Additional methods for decreasing power resistance network are also applied to reduce power nodes of RC network. Our methodology is applied to 6.4Gbps DDR5 products using 1y-nm DRAM process and succeeds in reducing RC network by over 88% and performing SI/PI co-simulation. This methodology can also be applied to analyze power supply induced jitter reflecting the off-chip environment for high correlation between simulation and the evaluation results on the silicon.