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Presentation

Static Timing and Power Analysis with Process Space Exploration
TimeMonday, July 11th5pm - 6pm PDT
LocationLevel 2 Exhibit Hall
Event Type
Engineering Track Poster
Engineering Tracks
Topics
AI
Back-End Design
Cloud
Embedded Systems
Front-End Design
IP
DescriptionSilicon level process search is very expensive and time-consuming. Thus, design-level DTCO can be a solution for the PPA optimization. However, library preparation for each DOE is also expensive. To overcome this, we enables accurate timing and power analysis without requiring expensive in situ library characterization. It requires one upfront characterization for augmented sensitivity data with respect to vth and mobility. Compared to SPICE, the error is within 2% over 99% paths. We applied this methodology to explore vth sweet spot using 4nm high performance CPU. We run 1458 STA runs and it takes 1 day using only 60 cores. At same frequency, 11% reduction in leakage power is achieved.