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Presentation

Compiler Approach for Automating Die2Die Trans-receiver HIP Placement for 3D-IC Design
TimeMonday, July 11th5pm - 6pm PDT
LocationLevel 2 Exhibit Hall
Event Type
Engineering Track Poster
Engineering Tracks
Topics
AI
Back-End Design
Cloud
Embedded Systems
Front-End Design
IP
Description3D-ICs design involves stacking of one or more Dies/Chiplets on top of a base Die. This requires perfect alignment of micro-bumps between different Dies. And, to simplify inter and intra die routing, Die2Die transceiver HIPs should be placed aligned to corresponding micro-bumps. This requires perfect synergy among various front-end and back-end design stakeholders like 3DIC package owner, RTL owners, micro-bump owners, full chip floor-planning owners, partition/section floorplan owners of the multiple Dies. Due to very high bandwidth requirements of Die2Die communication, the number of such HIPs can be close to or even more than ten thousand. More-over these HIPs need to be sprinkled across the Die which introduces its owner set of challenges. So, we need a systematic methodology accompanied by robust automation to ensure design consistency, route-ability, quality and to improve the floor planning and integration turn-around time. In this work, we will talk about various challenges and propose a systematic methodology and associated automation framework to solve these challenges. We will also present the results of deploying this proposal in actual designs on advanced technology nodes.