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Presentation

Cell EM aware Design Optimization
TimeMonday, July 11th5pm - 6pm PDT
LocationLevel 2 Exhibit Hall
Event Type
Engineering Track Poster
Engineering Tracks
Topics
AI
Back-End Design
Cloud
Embedded Systems
Front-End Design
IP
DescriptionCell EM aware design optimization is for validating the reliability condition inside cells while chip implementation. Design constraints for each cell types for satisfying reliability conditions can be characterized in the liberty as maximum allowable toggle rate. When the cell EM optimization is enabled, P&R tool is taking it as design constraint and fixing violations during CTS and routing. Our study shows that we achieve about 30% cell violation reduction with cell EM aware design flow.