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Presentation

Efficient Custom Logic P&R Flow using Virtual Hierarchy
TimeMonday, July 11th5pm - 6pm PDT
LocationLevel 2 Exhibit Hall
Event Type
Engineering Track Poster
Engineering Tracks
Topics
AI
Back-End Design
Cloud
Embedded Systems
Front-End Design
IP
DescriptionThis paper presents a new flow to reduce the layout TAT of custom logic for Analog/Mixed-Signal products. Custom logic has been designed with multiple hierarchy schematics and is usually developed by manual layout to meet tight requirements such as target area, design guidelines. The ideal solution to shorten the TAT is to use a custom placer and a router that reads schematics and generates layouts with required design constraints. However, the router can connect only current level nets since it is not able to see the net connectivity inside lower hierarchy blocks. Therefore, just applying a custom placer and a router to each hierarchy design was not effective to reduce TAT. In the proposed flow, newly adopted virtual hierarchy technology made it possible to create connectivity information of all hierarchies and enabled various design approaches. For example, a user can place custom logic designs 1) fully flattened, 2) partially flattened, 3) keeping original schematic hierarchies, and then route all open signals at level 0 referencing the connectivity information of total hierarchies extracted by virtual hierarchy. A pilot test result shows the proposed flow efficiently replaced time-consuming manual layout and the TAT reduction rate is 58%.