Enhancing Silicon Screening Using Optimized Clustering-Based SDD Vector
TimeTuesday, July 12th5pm - 6pm PDT
LocationLevel 2 Exhibit Hall
Event Type
Engineering Track Poster
Engineering Tracks
Back-End Design
Embedded Systems
Front-End Design
DescriptionAs high speed design operates at high frequency, it is not easy to have marginal timing slacks. Since small delay defect could cause a malfunction in the high speed design, it is very important to detect small delay defects. Conventional scan transition delay (TD) vector can hardly detect small delay defects. N-detect TD and path delay vector have appeared but they also have drawback in test vector volume. We propose a small delay defect (SDD) scheme which can detect additional small delay defect effectively with cost of reasonable test vector volume.
To reduce the SDD vector size, target fault optimization is performed. Based on the experimental result, we can reduce the target faults for SDD ATPG. For the reduced target faults, clustering-based SDD vector is generated to maximize the small delay defect screen ability. SDD vector analysis shows that the multiple clustering improves quality of SDD vector.
Legacy TD, 4N-detect TD, and SDD with/without clustering vectors are compared on target chips. Optimized clustering-based SDD vector shows best screening ability compared to other vectors in silicon test. Using the proposed SDD vector, screening out fail chip is much easier because it shows bigger gap between pass chip and fail chip.