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Presentation

Design Timing Effects of Layer-to-Layer Interconnect Skew
TimeMonday, July 11th5:10pm - 5:20pm PDT
LocationDAC Pavilion, Level 2 Exhibit Hall
Event Type
DAC Pavilion Gladiator Arena Poster Battle
Engineering Track Poster
Engineering Tracks
Topics
Back-End Design
Embedded Systems
Front-End Design
IP
DescriptionTraditional RC extraction methodologies generally set a certain combination of physical metal parameters to their extreme values to determine RC corners. These methods usually fail to capture possible layer-to-layer skew effects during manufacturing leading to potential robustness problems, especially in hold timing. Interconnect skew analysis captures design timing impacts of metal layer skews by considering all possible R, C combinations and their timing impact enabling designers to fix potential skew related issues and create more robust designs.