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Presentation

Dealing with Silicon Aging in Digital Implementation using Library Metrics
TimeTuesday, July 12th5pm - 6pm PDT
LocationLevel 2 Exhibit Hall
Event Type
Engineering Track Poster
Engineering Tracks
Topics
AI
Back-End Design
Cloud
Embedded Systems
Front-End Design
IP
DescriptionAging-degradation in IC has always been present. Aging can be evaluated via Aging-SPICE model. However, this SPICE model was not available as part of Fabrication providers’ PDK kit until recent years. With increased computational performance requirement with applications such as AI & Cryptography, we are often required to push the boundary of a particular process node beyond its nominal-voltage. Although we gain performance by increasing voltage, the aging-degradation is exponentially increased as the consequence. Therefore we need to accurately model our product’s aging during STA SignOff based on mission-profile provided by our customers. Conventionally, aging in digital circuits is implemented by applying a flat-derate to the entire design, this in effect reduces the product’s operation frequency. We have to over-design to account for the worst-case scenario usage from our customers.
For this presentation, we propose how to improve aging-derate accuracy in BE implementation. We partnered with Empyrean to develop a fast method to simulate aging degradation for all reference-cells in our standard-cell libraries. Using this information, we compared conventional flat-derate method with an accurate per-cell-derate obtained with Qualib software. This aging-metrics also allow us to create new applications such as deriving dont-use for poor-aging-performing cells,calculating HTOL aging-acceleration-factor, etc.