Integrating Liberty model validation, analysis, and visualization as part of library design and characterization
TimeTuesday, July 12th5:00pm - 6:00pm PDT
LocationLevel 2 Exhibit Hall
Event Type
Engineering Track Poster
Engineering Tracks
Back-End Design
Embedded Systems
Front-End Design
DescriptionStatic timing analysis (STA) engines rely heavily on high quality Liberty (.lib) models of standard cells, IOs, and other digital / analog macros, to provide accurate timing, power, and signal integrity validation for silicon designs. Today, due to considerations such as the need for statistical modeling, increased post-layout parasitic effects, and condition-based characterization, the average volume and complexity of modern .libs has grown 10x compared to 5 years ago.

Manual or script-based checking of .lib files can no longer reliably detect all .lib issues while keeping up with the availability of designs and revisions. To ensure correctness and accuracy of .libs, a comprehensive methodology for verifying and analyzing .libs must be integrated into the design and characterization process, and must have the intelligence to detect new categories of issues not explicitly specified by the user.

In this paper, we present a machine learning enabled .lib validation and analysis methodology utilized for pre-emptive error detection during the .lib production cycle, as well as examples of .lib issues that are uncovered and visualized using this method.