Thermal Aware Memory Controller Design with Chip Package System Simulation
TimeTuesday, July 12th5pm - 6pm PDT
LocationLevel 2 Exhibit Hall
Event Type
Engineering Track Poster
Engineering Tracks
Back-End Design
Embedded Systems
Front-End Design
DescriptionRapid technology evolution in semiconductor industry and demand for better performance leads to increased power consumption and higher power density in modern SoCs. This creates stringent design bottlenecks in power delivery design and thermal management resulting in thermal failures in the field. Traditional industry flow includes solving the SI/PI challenges first and then addressing thermal issues with guard-bands based on empirical experience. Such an approach assumes higher operating temperatures leading to higher design margins and design cost.

To address above issue, it is necessary to do chip aware system thermal design and system aware chip thermal design early in the SoC life cycle. This enables thermal co-simulation of chip and package, which provides realistic die temperature maps leading to better margins for thermal design and enables thermal aware on-die electromigration analysis.

In this paper, we present a novel methodology using Ansys CPS suite, to create Chip Thermal Model (CTM) from RedHawk which is subsequently included in Icepak simulation, to arrive at design level thermal conclusions that gave us deeper insights to save design time and cost. This method helped us predict 12 % higher power consumption due to leakage and identify thermal hotspots resulting in better sensor placement.