COMPUTE-IN-MEMORY SRAM ARRAY WITH NEW ENERGY EFFICIENT RECONFIGURABLE DATA SENSING TECHNIQUE FOR HARDWARE ACCELERATORS
TimeTuesday, July 12th5pm - 6pm PDT
LocationLevel 2 Exhibit Hall
Engineering Track Poster
DescriptionWith in-memory computing, calculations are performed directly in the memory array. SRAM-based Compute-in-Memory (CIM) involved activating multiple memory rows simultaneously and reading various logical functions from the corresponding selected rows. The sense amplifier (SA) plays an important role in the realization of the CIM. An Assist input based SA is proposed for performing in-memory Boolean logic computations in the static random access memories, in addition to the normal memory read operations. The proposed SA uses two auxiliary transistors to perform NAND and NOR operations under the use of only one SA, replacing the need for two SAs to perform the same operations. The 8+T differential SRAM has a separate decoupled read port which helps to achieve the CIM. The feasibility of the proposed circuit has been verified using detailed Monte-Carlo variation analysis in 65nm UMC technology. Our simulations indicate that 18% improvement in energy, 60% improvement in throughput leading to a reduction of 66% in energy delay product. There is 22% improvement in the area of SA.