Challenges of Integrating and Testing a Design with Multiple IP Vendors
TimeTuesday, July 12th5pm - 6pm PDT
LocationLevel 2 Exhibit Hall
Engineering Track Poster
DescriptionIn the interest of producing chip designs that have advanced function on an ever-decreasing design cycle, IP will be utilized from a number of IP vendors.
IP can range from interconnect IP, SerDes, memory interfaces such as HBM or DDR, PLLs, data converters, security functions as well as power management and more.
Challenges with IP from mixed vendors include integration, especially with high analog and mixed signal content, devising means for test, as well as the validation and simulation prior to tape out