Clock Scripting for Reliable Design Flow
TimeWednesday, July 13th5pm - 6pm PDT
LocationLevel 2 Exhibit Hall
Engineering Track Poster
DescriptionEDA vendor tool functionality is lacking for high performance/custom clock tree synthesis. We show ways to improve synthesis and repeatability of the clock tree insertion for custom trees, a feature that allows for full custom tree preservation and saving of semi-custom clock trees to save runtime on new netlist drops. We also so a method to clone critical clock logic to improve clock tree construction and overall results.