History based Physical Synthesis
TimeWednesday, July 13th5pm - 6pm PDT
LocationLevel 2 Exhibit Hall
Event Type
Engineering Track Poster
Engineering Tracks
Back-End Design
Embedded Systems
Front-End Design
DescriptionAggressive high performance design schedules coupled with competitive PPA targets typically lead to a large number of Physical Synthesis process iterations while design logic is being updated. Even with significant design changes, awareness of hard-to-close critical timing regions from prior runs may help make design timing closure more efficient. This may be especially useful in cases where the final timing critical regions are not revealed until later stages of timing optimization process, at which time only incremental and/or local techniques to improve timing may be preferred. We propose a novel method that extracts register-bounded critical region information from prior runs and takes advantage of this data in the current run to prioritize such regions starting from early stages of Physical Synthesis. More specifically, preference is given to such regions: during global placement steps to place critical paths optimally, during assignment of precious resources such as lower-vt and/or upper routing layers, as well as with targeted timing optimizations. A technique to merge any newly critical regions formed (not seen in prior runs) with known regions dynamically and improve overall timing QOR is also presented. Our experimental results using high-performance industrial designs show significant timing QoR improvements.