Efficient Low Power Isolation Handling for Pre-Silicon Emulation
TimeTuesday, July 12th5pm - 6pm PDT
LocationLevel 2 Exhibit Hall
Engineering Track Poster
DescriptionToday, SoCs are being designed with different power modes and the validation of these power modes at pre-silicon is necessary to catch any issues at an early stage rather than at silicon level. But the current emulation tools are inconsistent in isolation cell handling for low power (LP) emulations. To address this inconsistency, an efficient LP isolation handling for pre-silicon emulation through an algorithm-based insertion of isolation cells in RTL is presented.