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Presentation

Automated Timing Degradation Recovery in Incremental Tape-Out of High-Speed CPU Design
TimeWednesday, July 13th5pm - 6pm PDT
LocationLevel 2 Exhibit Hall
Event Type
Engineering Track Poster
Engineering Tracks
Topics
AI
Back-End Design
Cloud
Embedded Systems
Front-End Design
IP
DescriptionThis paper presents a novel approach for recovering timing degradations on incremental tape outs to maintain critical timing path-profile and to achieve desired power-performance targets. Design ECOs performed on data and clock components in incremental tape outs may cause degradations in certain timing arcs due to poorly auto-routed nets, increased load for drivers, aggressive hold violation fixes etc. The proposed method fixes the degraded timing paths by comparing reference and test timing paths and reverting the problematic changes as per the reference design topology. This approach helped to recover up to 90% of timing degradations and thus saving 2-3 weeks of manual efforts in fixing the degraded timing paths.