On-Chip embedded sensor in 18nm technology to monitor the effects of process variations on standard cells logic and interconnect delays
TimeWednesday, July 13th5pm - 6pm PDT
LocationLevel 2 Exhibit Hall
Engineering Track Poster
DescriptionTransistor and interconnect scaling has been used successfully in deep sub-micron CMOS technology to drive significant density and performance benefits in integrated circuits. Besides Transistors, Interconnects represent a much larger portion of the overall delay of integrated circuits today than in the past. Transistors and interconnects can vary in performance from lot to lot, wafer to wafer, and die to die, depending on fabrication process maturity and equipment tolerances. Thus, it is necessary to have some intelligence in SoC to detect and adapt to such variability. In this paper, an approach to the design of critical path representation sensors with interconnect is presented to monitor the effect of process variation on standard cell logic (transistors) and interconnect delays. Detailed explanations of the fundamental concept and design for 18nm technology are provided, along with simulation results. Speed binning, device screening, and compensation of SoCs can be done with this sensor.