Presentation
Process Monitoring Blocks - for Monitoring Analog Performance
TimeWednesday, July 13th5pm - 6pm PDT
LocationLevel 2 Exhibit Hall
Event Type
Engineering Track Poster
Engineering Tracks
AI
Back-End Design
Cloud
Embedded Systems
Front-End Design
IP
DescriptionThe effect of process variations has an extensive impact on the power, performance, and reliability of MOSFETS. As we know in Analog design is highly sensitive for parameters like VT of the MOS, resistance of Poly, vias and contacts and these are a major cause of design failure and yield loss. Adding to the complexity, these process variations can be local or across the chip or wafer-to-wafer, or even lot-to-lot. Silicon manufacturers usually put certain test structures in scribe line on selected wafers in each lot to observe and track the effects of process variation and DC characteristics of MOS devices, but these structures do not capture all the variation data. They also don’t provide explicit information to the designer about the corner the chip is running and hence to measure device Analog Performance on chip, there is a need of on chip Analog Process Monitoring Blocks (PMB).