Converging the “World’s Densest” PNR design on TSMC N5P - Beating Custom SRAM transistor densities in synthesized Place & Routed Design
TimeWednesday, July 13th5pm - 6pm PDT
LocationLevel 2 Exhibit Hall
Event Type
Engineering Track Poster
Engineering Tracks
Back-End Design
Embedded Systems
Front-End Design
DescriptionAn efficient, customized and automated place and route flow is needed to meet the stringent PPA targets with the fastest TAT of design closure. This is for a product targeting an extremely niche market with tight requirements on power & area. To hit the desired KPIs, extreme utilization targets (>90% std cell utilization) had to be set. Strict die & package area constraints were defined for product competitiveness.
We used multiple customizations (correct by construction execution and ECO cycles) in to the PNR recipes.
We needed to control design metric health throughout the implementation and ECO cycle.
Also, extreme utilization push also resulted in to reduced buffering and wire length hence a significant total power savings. We are going to explain all the key recipes to achieve >90% std cell utilization in this paper.