Technology co-optimization to mitigate the technology impact of context-based timing in standard Cell library
TimeWednesday, July 13th5pm - 6pm PDT
LocationLevel 2 Exhibit Hall
Event Type
Engineering Track Poster
Engineering Tracks
Back-End Design
Embedded Systems
Front-End Design
DescriptionIn lower technology CMOS devices impact of different layout effects on device parameters are very significant, due to proximity of devices. Layout effects include Well Proximity Effect, Shallow Trench Isolation/Length of Oxide Diffusion, metal environment in neighboring cells & routing done on SOC. These effects if not considered in characterization and SOC Signoff, will result into different delays at silicon as compared to CAD thereby resulting in functional failures and/or yield drop. Few technologies like P18 have specific performance booster (Continuous RX structure i.e., CRX) for PMOS devices. While It improves PMOS stress and boosts its performance by 15%, it also introduced strong dependency of cell delay on the placement environment, As the adjacent cells would have different width of RX or a break in RX.

In this paper we analyzed impact of these layouts’ effects on cell performance for P18 standard cells and explore ways to mitigate the same at library and Signoff level. Corners cases resulting from various effects are combined and replicated in two spice netlists for cell under consideration. This in turn is introduced in existing characterization and SOC Signoff flow to reduce the mismatch in CAD Signoff vs actual silicon delays