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Presentation

Design Intent Driven Analog Routing Methodology
TimeWednesday, July 13th5pm - 6pm PDT
LocationLevel 2 Exhibit Hall
Event Type
Engineering Track Poster
Engineering Tracks
Topics
AI
Back-End Design
Cloud
Embedded Systems
Front-End Design
IP
DescriptionTight Failure Rate Specification: 1ppm for Automotive and Industrial Application. Power Hungry IP and SOC: Demand of high speed application products in lower technology nodes is leading to increase in current density. Technology: Graphs show the impact on metal dimensions and current density with technology shrinkage. Cost by Reducing Metal Mask and to make product more competitive.

Virtuoso electrically driven design routing environment are the steps towards correct by construction routing driven by design intent. It provides an environment to consider analog design intents like matching, shielding, max resistance and high current and follow design rules during interactive routing. It is a solution that lets you take into consideration the current information and automatically resize wires and vias during interactive routing. For that we need of knowing current topology during layout phase to avoid EM-IR and design iterations. We need the final topology to be able to estimate the current going through all wires.

The proposed methodology assists the layout designer to achieve what he wants, while taking into account current density information. Finally, we are able to save design and layout turnaround time and its iterations by creating layout correct by electrical reliability factors like EM, IR, R and C.