Improving Power Grid IR drop with an automated layout enhancement flow
TimeWednesday, July 13th5pm - 6pm PDT
LocationLevel 2 Exhibit Hall
Engineering Track Poster
DescriptionIR drop an important part of power analysis in integrated circuit (IC) designs. It is a growing challenge for both design companies and foundries at advanced process nodes. Because power is impacted by many factors, a complete power optimization solution requires multiple solutions applied throughout the design flow. We introduce an analysis-based solution that is integrated with the place and route (P&R) flow to provide automated layout modifications that reduce IR drop without negatively impacting performance and area.
The key metrics for a P&R flow are focused on design performance, power, and area (PPA) goals. Designers first analyze a chip for power hotspots using IR drop simulation. This information is used to automatically make modifications to the layout based on a thorough understanding of the available white space and signoff DRC rules. These layout modifications reduce resistance (thereby reducing IR and EM issues).
The design flow will be presented as well as the Google’s results from their 5nm design. The solution reduced the number of instances above the acceptable IR drop threshold by ~90%. By eliminating the need for manual layout adjustments to correct the IR drop violations, the solution also significantly reduced the time pressure of final design closure.