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Presentation

FSDB based Self-Gating technique for Power saving and FEV Verification approaches
TimeWednesday, July 13th5pm - 6pm PDT
LocationLevel 2 Exhibit Hall
Event Type
Engineering Track Poster
Engineering Tracks
Topics
AI
Back-End Design
Cloud
Embedded Systems
Front-End Design
IP
DescriptionToday’s chip design focuses on highly power optimized circuit designs to increase the battery life. Self-Gating or XOR-Gating is an efficient way to optimize circuit power where register dynamic power is significant. ‘Clock Gating Least Efficient Registers (CGLAR)’, is a technique that caters to strengthening the existing ‘clock-gating enable’ and also targets the flops which didn’t have any enable in RTL or were dropped as a result of ‘min bank-width’ setting in synthesis. CGLAR which we are presenting in this paper is based on actual use-case via ‘FSDB’ activity. A good use-case eliminates all the guesswork and inefficiencies by conventional self-gating methods. Self-gating can induce functional failure. We at Intel, developed a formal verification paranoia flow which catches all the potential silicon failure and provide a suitable feedback for implementation. In this paper, we will illustrate this flow in detail.