Close

Presentation

Mitigation of Soft-Errors in Storage Elements through Layout and Circuit Design Techniques
TimeWednesday, July 13th5pm - 6pm PDT
LocationLevel 2 Exhibit Hall
Event Type
Engineering Track Poster
Engineering Tracks
Topics
AI
Back-End Design
Cloud
Embedded Systems
Front-End Design
IP
DescriptionSoft errors has become a critical reliability issue in modern semiconductor designs. This work proposes layout and circuit design mitigation techniques to reduce soft errors in storage elements adding area overhead and compromising on operating voltage. Most used cross coupled inverter circuit design is used to explain proposed techniques. Benefits from these techniques are quantified by simulating the design before and after implementing proposed techniques. Industry standard tool is used for design simulation. Device critical charge and LET threshold metrics are used to quantify the benefits. Simulation results show 24% and 85% improvement in device critical charge and LET threshold respectively, with implementation of proposed layout design technique. Similarly, proposed circuit design technique improves device critical charge and LET thresholds by ~184% and 218% respectively