A High-Accuracy Voltage-Aware-Timing Solution for HPC Design
TimeTuesday, July 12th5pm - 6pm PDT
LocationLevel 2 Exhibit Hall
Event Type
Engineering Track Poster
Engineering Tracks
Back-End Design
Embedded Systems
Front-End Design
DescriptionWith the evolution of process technology, the complexity and performance of chips are getting higher and higher. At the same time, the margin of the process is decreasing continuously, and the guard band sign-off approach may result in over-design. Therefore, it becomes more and more important to minimize the pessimism of the IR/timing and avoid over-fixing.
An advanced Voltage-Aware-Timing technology of RedHawk-SC and Prime-Time can help HPC design accurately quantify the interaction between voltage and timing, reduce the excessive margins and improve the IR coverage on critical timing paths and voltage sensitive paths. The technology has four main application scenarios:
● Timing-critical-paths aware IR-Drop analysis
● Voltage-sensitive-paths aware IR-Drop analysis
● IR-Drop aware timing analysis
● IR-Waiver analysis
These analysis can help optimize chip design and improve the Power-Performance-Area of the design and reduce the risk of silicon failures. In this paper, the following analysis were performed based on RedHawk-SC and Prime-Time, for a HPC design:
● Critical timing paths and voltage sensitive paths mining
● Timing-aware scenario generation and IR simulation
● Voltage-aware STA timing analysis
● STA result comparison with spice