Efficient Functional Sign off by Automatic Assertion Generation for RTL Building Blocks
TimeMonday, July 11th11am - 11:15am PDT
Location2010, Level 2
Event Type
Engineering Tracks
Front-End Design
Front-End Design
DescriptionWe address the functional verification of RTL designs based on recognizing that RTL is
conceived and implemented as assemblies of multiple hardware building blocks, each block
consisting of numerous logic gates, flip flops, memory cells, etc., and thereby fairly
complex. Despite said complexity, said building blocks have well-defined and widely
understood I/O semantics, allowing their categorization into a small number of repeatedly
used functional idioms. These building blocks are analogous to commonly used data
structures in software. Automatic inference is very challenging in production RTL
consisting of legacy code, third-party IP, and aggressive optimizations. We demonstrate
the feasibility of automatically inferring a large class of building blocks robustly
and efficiently in production RTL. This enables efficient and robust functional sign-off
because their well-defined semantics allows for uniform safety and coverage criteria to
be created for building blocks across a variety of implementations. Hence, we can automatically view a design as an interconnection of inferred building blocks and
emit implementation agnostic assertions for them. These assertions are applied in
functional verification by simulation or formal analysis. We have tested and deployed this
solution at Renesas with measurable improvements in our functional verification flow.
We highlight our case studies and experience.