Innovative Low Power UPF GENERATION and HIERARCHICAL MODELING OF Custom blocks
TimeWednesday, July 13th1:45pm - 2pm PDT
Location2010, Level 2
Event Type
Engineering Tracks
Front-End Design
Front-End Design
DescriptionCustom blocks UPF coding and Low Power Static Verification is critical to the Overall Power Intent Methodology. UPF flow is complimentary to the other Electrical Rule Checks (ERC) and Design Simulation runs. Due to this, there is a need to code custom block UPF efficiently. In addition, there needs to be a good Modeling and Abstraction of the fully verified lower custom blocks. In this paper, a novel innovative approach is shown to auto-generate UPF from a custom block schematic. In addition, there is an approach to auto-black box lower-level blocks with intent preserved once they are verified. Finally, a summary is shown on how the custom block UPF flow is complementary to the ERC checks and adds coverage to the overall block level verification.