Extracting Source of Unknown Values in Transistor-level Logic Simulation
TimeTuesday, July 12th10:30am - 10:45am PDT
Location2010, Level 2
Event Type
Engineering Tracks
Front-End Design
Front-End Design
DescriptionTransistor-level design has been used for its advantages regarding design flexibility. Traditional transistor-level design is not based on RTL design flow for maintaining its flexibility, time-based logic simulation can only be used as functional verification and various types of unknown signals those should be verified for design robustness and analysis coverage are generated. In this paper, the possible types of unknown sources and the optimal algorithm for extracting sources of unknown signals are presented. Experimental result shows the number of unknown signals is decreased to 1% which are unknown sources those can be regarded as meaningful circuits generating unknown signal within 2 days for .5 milliseconds simulation.