Machine Learning Based Abnormal Simulation Detector in SoC Verification
TimeMonday, July 11th1:30pm - 1:45pm PDT
Location2010, Level 2
Event Type
Engineering Tracks
Front-End Design
Front-End Design
DescriptionSoC designs get bigger and more complex every year. Even though not enough time for SoC Verification is given in SoC development stages, it is necessary to finish SoC Verification within SoC Design phase. To meet the schedule, unnecessarily spend time and cost in SoC Verification need to be reduced. Especially in abnormal simulations caused by simulation hang, a lot of computing powers and resources are spent unnecessarily. With traditional SoC Verification simulation method, when a lot of simulations are running like full-chip level regression tests, it's difficult to tell if what simulations are hung. Our goal is to reduce these unintentionally spent time and cost. The proposed Abnormal Simulation Detector is an innovative Machine Learning based framework to reduce time and cost in SoC Verification. we present this Abnormal Simulation Detector which enables early detection of abnormal situations, improvement of debugging progress, reduction of consumed time and resources, test planning with expected simulation run-time from ML Model and easy detection of simulation hang in full-chip level regression tests.