Fully Automated Modular Method for Comprehensive Low Power Simulation Coverage
TimeWednesday, July 13th2pm - 2:15pm PDT
Location2010, Level 2
Event Type
Engineering Tracks
Front-End Design
Front-End Design
DescriptionAdvanced markets like IOT, and embedded consumer, industrial and automotive drive complex power managed system design with integrated mixed-signal, RF and power management contents.

Designs with large number of applications with lowest power consumption and on time delivery are the key contributors in winning the market. While technology scaling enables more complex functionality on SoCs, power consumption increases significantly and mandates the reduction of active and standby power. Battery powered SoCs require considerably more aggressive power reduction techniques. To address these challenges we need advanced low power techniques seamlessly supported at IP and system specification, design, integration, verification and sign-off stages for both custom and semi-custom design contents.

These SoCs have large number of soft, hard and mixed-signal IPs with power reduction techniques such as power gating, voltage domains and clock gating implemented at both IP and SoC levels. In addition to SoC power management (PM) complexity increases as the need for state retention in the presence of power gating for several IPs to meet system level performance challenges. To achieve entitled power with such complex and advanced design techniques, conventional verification techniques especially those related to power connectivity and functional dependence on power/voltage domain partitions are incapable of delivering required verification quality, coverage and comprehensiveness.

Current verification flows lack meaningful low power coverage quantification. In the absence of the same, the comprehensiveness and completeness of low power verification is subjective based on manual reviews, manual specification and system modes traceability. In the recent past there have been silicon issues in power managed mixed-signal SoCs related to low power implementation bugs. In this paper, a comprehensive coverage quantification methodology defined for mixed-signal aware, low power aspects like isolation, retention and level shifting which includes all possible data states, all special sequence requirements associated with advanced retention functions (clock, reset, preset conditions), different reset behaviors at cold power-up and power-up from low power mode(s) under right power state(s) of related switched power domains. Results of application of the methodology for an industrial power managed mixed-signal embedded processing SoC is shared.