Verifying Security Countermeasures for side channel fault attacks, in an Integrated Circuit at RTL or Gate level, using Fault Attack Simulation (FAS)
TimeTuesday, July 12th11am - 11:15am PDT
Location2010, Level 2
Event Type
Engineering Tracks
Front-End Design
Front-End Design
DescriptionSecurity of electronic systems is a major concern, especially in applications like credit cards, automotive electronics, IOT devices, etc. An adversary can extract the secret information to access trusted operations, thereby posing safety or financial threats. Hence protecting against these attacks is becoming a key part of Cybersecurity by Design.

Hackers have developed multiple techniques to extract the security assets hidden in IC’s, using various types of side-channel and fault injection attacks. However, pre-silicon verification of the protection measures by simulating Side Channel and Fault Injection attacks remains an unsolved problem, and often expensive, post-silicon, lab-based solutions are used.

In Automotive Electronics, verifying these countermeasures for various threat scenarios is highly important to avoid safety, privacy, and financial-loss. ISO/SAE 21434 recommends cybersecurity issues to be discovered and resolved from the earliest stage in the development lifecycle.

This paper presents Optima’s FAS solution, based on Optima’s ultra-fast Fault Injection Engine. FAS models the different attack scenarios, in the design (RTL or Gate Level Netlist). During FAS, millions of fault-attacks are simulated to check the effectiveness of countermeasures, and weaknesses are reported for the user to improve protection. This paper also reports the results from a recent case study performed.