System and method to improve RTL quality by using backend tools flows and methodology for RTL Handoff
TimeMonday, July 11th2pm - 2:15pm PDT
Location2010, Level 2
DescriptionRegister Transfer Level (RTL ) is the result of coding design specification. Poor RTL quality can cause expensive loops between RTL and layout design. In today’s design methodology, SOC building blocks (IP/Partitions) are designed and optimized per their fundamental specifications. “What-if” analysis is required on these blocks to swiftly tune them further as per the above-described dimensions.
An insight into backend physical and electrical parameters is very important to make effective choices for building blocks and improve design quality. Corrective actions at RTL design stage are less expensive, easier to implement and facilitate better product quality. In the proposed system and method, we perform technology and physically aware RTL verification by using backend tools flow and methodology in RTL design environment. This approach significantly improves RTL design, removes pessimism and increases predictability in design convergence. The application of this correct-by-construction method improves RTL quality significantly and turn around time by several weeks.