RTL Design Security Verification for Resisting Power Side-Channel Analysis
TimeTuesday, July 12th11:15am - 11:30am PDT
Location2010, Level 2
Event Type
Engineering Tracks
Front-End Design
Front-End Design
DescriptionA cryptographic module is potentially vulnerable to side-channel (SC) attacks on power supply current flow and electromagnetic (EM) emission. Simulation-based SC leakage analysis will accelerate the design, verification and validation of SC resiliency before the tape out of an integrated circuit (IC) chip. Fast RTL power trace simulation enables to assess SC countermeasure effectiveness early in the design flow, at RTL stage. This work proposes a new time-based power simulation with a simulation engine dedicated for the capability of multi-million or even billion-cycle long vectors as well as for the accuracy of power supply current waveforms, and enables fast power side-channel leakage analysis. We also propose an information tracking methodology which helps a designer to find out security critical registers. The SC leakage from four different cryptographic modules, including an unprotected secret key crypto, two protected secret key crypto cores, and a protected public key crypto, are evaluated with the proposed SC leakage simulation methodology. The novel RTL power profiling engine demonstrates the RTL power noise simulation of crypto cores with billion cycles (or millions of test inputs) in 1 hour and verifies SC resiliency in the exploration of crypto architecture.