A Novel Analog Centric Automated Verification Methodology Driven by State Diagram Approach
TimeMonday, July 11th11:45am - 12pm PDT
Location2010, Level 2
DescriptionState diagrams are a powerful tool in capturing the dynamic behavior of a device, characterizing the different states of operation and the legal transitions between these states. The methodology outlined below captures the essence of state diagram within the mixed signal verification environment helping to model the behavior of the device under the applied test stimulus using a finite state machine. This approach helps to easily understand the functioning of the part under different stimuli, catch unexpected state entries as well as enable the use of mature tools to arrive at a coverage metric thereby increasing the thoroughness and confidence of verification. An automation wrapper is developed which speeds up the implementation as well as integration of the FSM flow with checker verification. The solution gives a comprehensive error report that details Pass/Fail status of the checks incorporated, a comparison Excel output that highlights differences in the state sequence across corners and all the critical coverage information.