Memory Read Yield Estimation Using High Sigma Monte Carlo
TimeMonday, July 11th3:30pm - 3:45pm PDT
Location2012, Level 2
DescriptionWith ever-shrinking CMOS technology, particularly in nanometer regime, when devices are operating at ultra-low voltages, device variation poses major challenge SRAM designs that uses smallest feature devices. Achieving good yield on silicon demands high sigma qualification (>5-sigma) based on the application and total capacity used in the SoC. Non-Gaussian nature of variations puts a limitation on existing methodologies due to inaccuracies resulting from Gaussian extrapolation and approximations. The turn-around time to address this problem demands much larger simulation resources and requires few days (as per mission profile) for the analysis.
In this paper, we discuss how to estimate Read Yield of a SRAM IP using High Sigma Monte Carlo technique available in EDA tools today. This flow involves the following steps –
1) Perform High Sigma Monte Carlo (HSMC) analysis for bitcell read current (Iread) for different target sigma values. This creates a corresponding weak bitcell model.
2) Import the weak bitcell model into full memory instance and measure the corresponding VDiff (differential voltage available for sensing).
Steps (1) and (2) are used to help in estimating Memory Read Yield.
The proposed flow help us to cut down Read Yield Estimation process from 5 days to ½ day.