Verifying I/O Designs Using Symbolic Simulation to Increase Design and Model Robustness
TimeMonday, July 11th4pm - 4:15pm PDT
Location2012, Level 2
Event Type
Engineering Tracks
DescriptionInterface IPs are an important part of any integrated circuit design that needs to communicate with the outside world or other integrated circuits. While these Interface protocols (e.g., HDMI, SPI, I2C, I3C, etc.) open gates to connect different compute systems, their complexity brings a vast amount of verification challenges. Out of many design views of IO libraries, the logical views have special importance as it defines the basic function of the design. If not verified to the best possible extent, it can fail to perform the very basic task for which an IP was designed in the first place. Broken functionality leads to one of the heaviest costs a design house may pay in terms of silicon failures.

Symbolic simulation provides unique and powerful solutions to the plethora of technical challenges faced by logic verification engineers of interface IPs. The Synopsys ESP uses symbolic simulation technology to offers high-quality equivalence checking for full-custom designs.

While Synopsys ESP is mostly used for the equivalence checking in Standard cells and Memory design, we are using it for interface IPs and showcasing the challenges faced and workaround used in adapting the tool to the complex logic of interface IPs and showcasing the advantage it brought along.