Frequency synthesizers with a purpose in advanced process technologies
TimeMonday, July 11th4:30pm - 4:45pm PDT
Location2012, Level 2
DescriptionThe connectivity required for high performance computing, automotive, and Internet of Things (IoT) applications places stringent specification requirements on some of the most critical components such as Phase-Locked Loops (PLL). PLLs are used to demodulate wireless signals, enable high-speed SerDes channels, perform skew cancellation for phase alignment, clean up noisy reference clocks, synthesize stable frequencies with high resolution, or distribute precisely timed clocks in digital circuits. Architecture choices for various building blocks and the PLL system is key in shaping clock stability, noise and jitter given area and power constraints.
Analog Bits is the leader in developing and delivering low-power integrated clocking, sensors, and interconnect IP that are pervasive in virtually all of today’s semiconductors. Analog Bits uses Siemens EDA Analog FastSPICE Platform (AFS) for nanometer circuit verification and sign-off. With AFS, designers are able to perform large analog circuit simulation and noise analysis with nanometer SPICE accuracy while increasing their productivity. AFS is certified in the advanced FinFET process nodes with all major foundries including 7nm, 5nm and 3nm process nodes. Each advanced node provides more PPA (Power / Performance / Area) benefits over the prior one empowering IC developers to innovate more complex designs.
As an example of such success, this paper describes the design, verification, and silicon data of an Analog Bits high performance PLLs fabricated in advanced FinFET process technologies and verified using the Siemens EDA Analog FastSPICE Platform.
In this paper, we will describe the challenges associated with achieving silicon-accurate design and verification results of a wide portfolio of PLL architectures fabricated in advanced processes. We will show results of AFS transient results and silicon correlation of important parameters such as power < 5mW at 10GHz VCO speeds, transient noise results of high performance of 20 GHz C2C PLL with RJ < 600fs for PLL’s. Analog Bits has used the same design methodology in the tape-out of N3 IP’s.