A hierarchical and tractable Mixed Signal verification methodology for first-generation Analog AI Processors
TimeMonday, July 11th4:45pm - 5:00pm PDT
Location2012, Level 2
Event Type
Engineering Tracks
DescriptionIn the AI hardware industry, everyone is asking whether there is a way to improve matrix multiplication, which is the most fundamental and compute-intensive operation in machine learning and deep neural networks (DNNs). In recent years, several hardware architectures have evolved to accelerate matrix multiplication, however, all of them have one thing in common, they all took the digital approach. Digital processing has hit a wall with respect to executing DNN MAC operations with the desired energy efficiency. A new analog computing approach is presented here which takes advantage of analog compute-in-memory (CIM) techniques. Logic signals are driven via digital-to-analog converters, through a flash memory array, which stores neural network weights, and the result is captured through analog-to-digital converters. Analog compute is the ideal approach for AI processing, because of its ability to operate using much less power at a higher speed and with faster framerates and lower latencies but implementing and verifying analog designs can be a daunting task. This first chip is made up of 76 tiles consisting of 19,456 ADCs, 83 RISC-V cores, and 14 charge-pumps resulting in a very complex verification problem. In this paper, we propose a hierarchical and tractable design & verification methodology from block to subsystem to full-chip mixed-signal simulation which addresses many verification challenges. Simulation results using Siemens AMS tools are discussed showing close correlation with silicon data.