Architecting DDR5 DRAM Caches for Non-Volatile Memory Systems
TimeThursday, July 14th1:53pm - 2:15pm PDT
Location3005, Level 3
SoC, Heterogeneous, and Reconfigurable Architectures
DescriptionWith Intel’s Optane DIMM release, Non-Volatile Memories (NVMs) are emerging as a promising technology for large-scale memory systems. To incorporate the existing DRAM subsystem, Optane provides a memory mode where DRAM serves as a data cache for Optane. It achieves good performance for cache hit, but exacerbates the already high latency for cache miss. In this paper, we inspect new features in DDR5 to better support the DRAM cache design for Optane. Specifically, we leverage the two-level ECC scheme in DDR5 to construct a narrower channel for tag probing and a new operation for fast cache replacement.