Silicon Validation of LUT-based Logic-Locked IP Cores
TimeThursday, July 14th4:30pm - 4:50pm PDT
Location3000, Level 3
Design Verification and Validation
DescriptionTo secure the hardware against various hardware security threats, various logic obfuscation mechanisms have been proposed. However, the insertion of the obfuscation primitives requires modification to the standard physical design flow. Moreover, the estimation of resiliency against various attacks is hard to quantify and has not been studied.