HIMap: A Heuristic and Iterative Logic Synthesis Approach
TimeTuesday, July 12th3:30pm - 3:50pm PDT
Location3007, Level 3
RTL/Logic Level and High-level Synthesis
DescriptionWe propose a novel heuristic and iterative flow HIMap for deterministic logic synthesis, consisting of three high-level stages: delay-oriented stage, delay-constrained area-recovery stage, and high-effort area reduction stage. These three stages follow the same template, in which we introduce a simple but effective heuristics to iteratively improve netlist PPA. Two nested template-like iterations with local searching and early stopping are utilized to generate dynamic sequence for different circuits and iteration stages. HIMap refreshes best 16 results out of 40 EPFL Combinational benchmarks for LUT-6 area and level. Especially, HIMap reduces LUT-6 levels by 11.64% to 20.33% in several arithmetic benchmarks.