SMART: On Simultaneously MArching RaceTracks to Improve the Performance of RaceTrack-based Main Memory
TimeWednesday, July 13th4:50pm - 5:10pm PDT
Location3004, Level 3
Event Type
Research Manuscript
Embedded Memory, Storage and Networking
Embedded Systems
DescriptionRaceTrack Memory (RTM) is a promising alternative of modern main memory sub-systems, in terms of both density and energy efficiency. However, the nature of RTM (i.e., shift-before-access) introduces considerable overheads to latency. Moreover, we characterize and observe that such nature incurs more performance overheads, since there exists a mismatch between (i) the granularity of RTM access/shift operations (i.e., one Domain Block Cluster at a time (DBC)) and (ii) common access patterns in modern RTM-based Main Memory. We propose a novel mechanism called \mechanism{} to improve the performance of RTM-based Main Memory.